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A-V EZ-Extender Hardware Reference
Table 2-5. PPI Clock Setup Jumper Results
Jumper
JP4.1/2
JP4.3/4
JP4.5/6
JP4.7/8
Result
Connects EXT_VID_CLK to an onboard 27 MHz oscillator. For more informa-
tion about the EXT_VID_CLK signal, see the description of JP4.3/4 .
Connects PPI0_CLK to the EXT_VID_CLK net. The EXT_VID_CLK net is the
external clock, which drives the input clock of all the camera module interface
connectors, plus the flat panel display connector. Depending on the installation
of the other JP4 jumpers, EXT_VID_CLK can be generated by the PIXEL_CLK
net, the VDEC_CLKOUT net, a socket ( U8 ), or the onboard 27 MHz oscillator.
Connects VDEC_CLKOUT to PPI0_CLK ; VDEC_CLKOUT drives the PPI0 clock
when the video decoder is used.
Connects the PIXEL_CLK net, which is an output from the three camera module
interfaces, to PPI0_CLK .
PPI0 D8 –15 Enable Jumper (JP5.1/2)
The JP5.1/2 jumper, when not installed, disables the upper 8-bits of the
PPI0 data bus. This allows the signals connected to the upper 8-bits of the
PPI data bus on the EZ-KIT Lite to be used elsewhere.
To disable and reuse the upper 8-bits of the VID_IN and PPI0 data busses,
install the JP5.1/2 jumper.
VID_OUT Data Bus Control Jumpers (JP5.3/4,
JP5.5/6)
The JP5.3/4 and JP5.5/6 jumpers are used together to set up the direc-
tion of, as well as to enable or disable, the drivers driving the VID_OUT data
bus. Table 2-6 shows the results of different combinations of the JP5.3/4
and JP5.5/6 jumpers.
Blackfin A-V EZ-Extender Manual
2-11
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